The generation and control of multiple clock signals operating at one frequency, having distributed phases, and having substantially equal phase spacing is critical to the design of many high-performance, high-speed chip-to-chip interconnect systems. Some interconnect systems use just two phases: the rising and falling edge of a single, very high-speed clock. However, accurately controlling the duty-cycle of such a high-speed clock may be difficult. Also, it becomes necessary (and also difficult) to operate the high speed clock at a high frequency equal to one-half the data rate. Other interconnect systems use 4, 5, 8, 10 or more clock phases in their transmitter, receiver, or both. Because there are more clock phases, these multi-phase clocks can operate at a lower frequency equal to a smaller fraction of the data rate, such as one-fourth, one-fifth, one-eighth, or one-tenth, for example. Many chip-to-chip interconnect systems make use of multi-phase clock generators because of the lower frequency of the clocks required to support a given data rate.